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- 2022
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Mark
Spatially Coupled Serially Concatenated Codes: Performance Evaluation and VLSI Design Tradeoffs
(
- Contribution to journal › Article
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Mark
An Application Specific Vector Processor for Efficient Massive MIMO Processing
(
- Contribution to journal › Article
- 2021
-
Mark
Power Scaling Laws for Radio Receiver Front Ends
(
- Contribution to journal › Article
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Mark
An active-under-coil RFDAC with analog linear interpolation in 28-nm CMOS
(
- Contribution to journal › Article
- 2020
-
Mark
An N-Path Filter Design Methodology With Harmonic Rejection, Power Reduction, Foldback Elimination, and Spectrum Shaping
2020) In IEEE Transactions on Circuits and Systems I: Regular Papers(
- Contribution to journal › Article
- 2019
-
Mark
Improving Receiver Close-In Blocker Tolerance by Baseband Gm-C Notch Filtering
(
- Contribution to journal › Article
- 2018
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Mark
An Area-Efficient On-Chip Memory System for Massive MIMO Using Channel Data Compression
2018) In IEEE Transactions on Circuits and Systems I: Regular Papers(
- Contribution to journal › Article
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Mark
A 128 kb 7T SRAM Using a Single-Cycle Boosting Mechanism in 28 nm FD–SOI
(
- Contribution to journal › Article
- 2017
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Mark
An Adaptive QR Decomposition Processor for Carrier Aggregated LTE-A in 28 nm FD-SOI
2017) In IEEE Transactions on Circuits and Systems I: Regular Papers(
- Contribution to journal › Article
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Mark
A general theory of phase noise in transconductor-based harmonic oscillators
(
- Contribution to journal › Article
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Mark
Two Tunable Frequency Duplexer Architectures for Cellular Transceivers
2017) In IEEE Transactions on Circuits and Systems I: Regular Papers(
- Contribution to journal › Article
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Mark
On the Remarkable Performance of the Series-Resonance CMOS Oscillator
2017) In IEEE Transactions on Circuits and Systems I: Regular Papers(
- Contribution to journal › Article
-
Mark
Compressed Level Crossing Sampling for Ultra-Low Power IoT Devices
(
- Contribution to journal › Article
- 2016
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Mark
Ultra Low Voltage Synthesizable Memories: A Trade-Off Discussion in 65nm CMOS
(
- Contribution to journal › Article
- 2015
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Mark
Low Power Analog and Digital (7,5) Convolutional Decoders in 65 nm CMOS
(
- Contribution to journal › Article
-
Mark
A Heterogeneous Reconfigurable Cell Array for MIMO Signal Processing
(
- Contribution to journal › Article
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Mark
Energy Efficient Group-Sort QRD Processor with On-line Update for MIMO Channel Pre-processing
(
- Contribution to journal › Article
- 2014
-
Mark
Improved Matching-Pursuit Implementation for LTE Channel Estimation
(
- Contribution to journal › Article
-
Mark
Energy-Efficient Soft-Input Soft-Output Signal Detector for Iterative MIMO Receivers
(
- Contribution to journal › Article
- 2013
-
Mark
Hardware architecture of IOTA pulse shaping filters for multicarrier systems
(
- Contribution to journal › Article
-
Mark
An N-Path Enhanced-Q Tunable Filter With Reduced Harmonic Fold Back Effects
(
- Contribution to journal › Article
- 2012
-
Mark
An Analysis of 1/f Noise to Phase Noise Conversion in CMOS Harmonic Oscillators
(
- Contribution to journal › Article
-
Mark
Area-efficient configurable high-throughput signal detector supporting multiple MIMO modes
(
- Contribution to journal › Article
- 2011
-
Mark
Multicarrier faster-than-Nyquist transceivers: hardware architecture and performance analysis
(
- Contribution to journal › Article
- 2010
-
Mark
Reduction of substrate noise in sub clock frequency range
(
- Contribution to journal › Article
- 2009
-
Mark
A time-variant analysis of fundamental 1/f3 phase noise in CMOS parallel LC-tank quadrature oscillators
(
- Contribution to journal › Article
- 2008
-
Mark
Optimization and implementation of a Viterbi decoder under flexibility constraints
(
- Contribution to journal › Article
-
Mark
Low-Complexity Binary Morphology Architectures with Flat Rectangular Structure Elements
(
- Contribution to journal › Article
- 2006
-
Mark
A time-variant analysis of the 1/f2 phase noise in CMOS parallel LC-tank quadrature oscillators
(
- Contribution to journal › Article