Digital ASIC-lup-obsolete
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- 2011
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Mark
Improved memory architecture for multicarrier faster-than-Nyquist iterative decoder
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Level of Confidence Evaluation and Its Usage for Roll-back Recovery with Checkpointing Optimization
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Scheduling Tests for 3D Stacked Chips under Power Constraints
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Test Cost Modeling for 3D Stacked Chips with Through-Silicon Vias
(2011) Swedish System-on-Chip Conference, SSoCC 2011
- Contribution to conference › Paper, not in proceeding
-
Mark
Inverter circuits based on vertical InAs nanowire MOSFETs
(2011) Swedish System-on-Chip Conference, SSoCC 2011
- Contribution to conference › Paper, not in proceeding
-
Mark
Detecting multi-mode MIMO: signals algorithm and architecture design
- Contribution to conference › Paper, not in proceeding
-
Mark
Beyond von Neumann: weakly programmable processor arrays and their programming
(2011) First International Software Technology Exchange Workshop
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
A VLSI implementation of logarithmic and exponential functions using a novel parabolic synthesis methodology compared to the CORDIC algorithm
(2011) European Conference on Circuit Theory and Design (ECCTD 2011)
- Contribution to conference › Paper, not in proceeding
-
Mark
Low Power and Area Efficient Implementation of a Real-Time AF Detection Algorithm in 130 nm CMOS
(2011) Swedish System-on-Chip Conference, SSoCC 2011
- Contribution to conference › Paper, not in proceeding
-
Mark
An Analog (7,5) Convolutional Decoder in 65 nm CMOS for Low Power Wireless Applications
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
