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- 2023
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Mark
An LO phase shifter with frequency tripling and phase detection in 28 nm FD-SOI CMOS for mm-wave 5G transceivers
(
- Contribution to journal › Article
- 2021
-
Mark
An ultra-low power high-precision logarithmic-curvature compensated all-CMOS voltage reference in 65 nm CMOS
(
- Contribution to journal › Article
- 2019
-
Mark
A high precision logarithmic-curvature compensated all CMOS voltage reference
(
- Contribution to journal › Article
- 2017
-
Mark
System simulations of a 1.5 V SiGe 81-86 GHz E-band transmitter
(
- Contribution to journal › Article
- 2016
-
Mark
A continuous-time delta-sigma ADC with integrated digital background calibration
(
- Contribution to journal › Article
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Mark
A wide band fractional-N digital PLL with a noise shaping 2-D time to digital converter for LTE-A applications
(
- Contribution to journal › Article
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Mark
A 2.8-to-5.8 GHz harmonic VCO based on an 8-shaped inductor in a 28 nm UTBB FD-SOI CMOS process
(
- Contribution to journal › Article
- 2015
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Mark
A 28 GHz SiGe PLL for an 81-86 GHz E-band beam steering transmitter plus an I/Q phase imbalance detection and compensation circuit
(
- Contribution to journal › Article
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Mark
A low-power 2nd-order CT delta-sigma modulator with an asynchronous SAR quantizer
(
- Contribution to journal › Article
- 2014
-
Mark
A 1V power amplifier for 81-86 GHz E-band
(
- Contribution to journal › Article
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Mark
A 60 GHz receiver front-end with PLL based phase controlled LO generation for phased-arrays
(
- Contribution to journal › Article
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Mark
A low-power 2nd-order CT delta-sigma modulator with a single operational amplifier
(
- Contribution to journal › Article
- 2013
-
Mark
Tunable wideband SAW-less receiver front-end in 65 nm CMOS
(
- Contribution to journal › Article
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Mark
A 2.7-6.1 GHz CMOS local oscillator based on frequency multiplication by 3/2
(
- Contribution to journal › Article
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Mark
A 2-D GRO Vernier Time-to-Digital Converter with Large Input Range and Small Latency
(
- Contribution to journal › Article
-
Mark
Theory and Design of a CT Delta Sigma Modulator with Low Sensitivity to Loop-Delay Variations
(
- Contribution to journal › Article
-
Mark
A 0.7 to 3 GHz wireless receiver front end in 65-nm CMOS with an LNA linearized by positive feedback
(
- Contribution to journal › Article
-
Mark
Introduction to the Special Issue on 29th NORCHIP Conference
(
- Contribution to journal › Debate/Note/Editorial
- 2012
-
Mark
A Continuous Time Delta-Sigma Modulator with Reduced Clock Jitter Sensitivity through DSCR Feedback
2012) In Analog Integrated Circuits and Signal Processing(
- Contribution to journal › Article
- 2011
-
Mark
Time-variant analysis and design of a power efficient ISM-band quadrature receiver
(
- Contribution to journal › Article
-
Mark
Design and analysis of an ultra-low-power LC quadrature VCO
(
- Contribution to journal › Article
-
Mark
A PLL based 12 GHz LO generator with digital phase control in 90 nm CMOS
(
- Contribution to journal › Article
-
Mark
A 5GHz 90-nm CMOS all digital phase-locked loop
(
- Contribution to journal › Article
-
Mark
A BiCMOS single ended multiband RF-amplifier and mixer with DC-offset and second order distortion suppression
(
- Contribution to journal › Article
- 2010
-
Mark
A technique for improving gain and noise figure of common-gate wideband LNAs
(
- Contribution to journal › Article
- 2009
-
Mark
Analysis of a high frequency and wide bandwidth active polyphase filter based on CMOS inverters
(
- Contribution to journal › Article
- 2007
-
Mark
Characterization of CMOS Impedance Tuning Unit
(
- Contribution to journal › Article
-
Mark
A polyphase filter based on CMOS inverters
(
- Contribution to journal › Article
-
Mark
Linearity of bulk-controlled inverter ring VCO in weak and strong inversion
(
- Contribution to journal › Article
-
Mark
A toroidal inductor integrated in a standard CMOS process
(
- Contribution to journal › Article
- 2006
-
Mark
Full oscillation cycle phase noise analysis of differential CMOS LC oscillators
(
- Contribution to journal › Article
-
Mark
An ultra low voltage, low power, fully integrated VCO for GPS in 90 nm RF-CMOS
(
- Contribution to journal › Article
- 2005
-
Mark
A distributed capacitance analysis of co-planar inductors for a CMOS QVCO with varactor tuned buffer stage
(
- Contribution to journal › Article
-
Mark
Reduced impact of induced gate noise on inductively degenerated LNAs in deep submicron CMOS technologies
(
- Contribution to journal › Article
- 2004
-
Mark
A single-stage direct interpolation multiphase clock generator with phase error averaging
(
- Contribution to journal › Article
- 2002
-
Mark
A voltage-translinear based CMOS signal component separator chip for linear LINC transmitters
(
- Contribution to journal › Article
- 2000
-
Mark
A 2.4-GHz CMOS monolithic VCO with an MOS varactor
(
- Contribution to journal › Article
-
Mark
A chip for linearization of RF power amplifiers using predistortion based on a bit-parallel complex multiplier
(
- Contribution to journal › Article
- 1999
-
Mark
Power Reduction in Custom CMOS Digital Filter Structures
(
- Contribution to journal › Article
-
Mark
An inductorless 300MHz wideband CMOS power amplifier
(
- Contribution to journal › Article
-
Mark
A digitally controlled shunt capacitor CMOS delay line
(
- Contribution to journal › Article
- 1997
-
Mark
A novel class AB CMOS power amplifier
(
- Contribution to journal › Article