Digital ASIC-lup-obsolete
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- 2011
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Mark
Test Cost Modeling for 3D Stacked Chips with Through-Silicon Vias
(2011) Swedish System-on-Chip Conference, SSoCC 2011
- Contribution to conference › Paper, not in proceeding
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Mark
A VLSI implementation of logarithmic and exponential functions using a novel parabolic synthesis methodology compared to the CORDIC algorithm
(2011) European Conference on Circuit Theory and Design (ECCTD 2011)
- Contribution to conference › Paper, not in proceeding
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Mark
Low Power and Area Efficient Implementation of a Real-Time AF Detection Algorithm in 130 nm CMOS
(2011) Swedish System-on-Chip Conference, SSoCC 2011
- Contribution to conference › Paper, not in proceeding
-
Mark
An Analog (7,5) Convolutional Decoder in 65 nm CMOS for Low Power Wireless Applications
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Formation of the axial heterojunction in GaSb/InAs(Sb) nanowires with high crystal quality
- Contribution to journal › Article
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Mark
Test Scheduling and Test Access Optimization for Core-Based 3D Stacked ICs with Through-Silicon Vias: poster
(2011) IEEE European Test Symposium (ETS), 2011
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2010
-
Mark
An iterative decoder for multicarrier Faster-than-Nyquist signaling systems
(2010) IEEE International Conference on Communications, ICC 2010
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
High Frequency Performance of Vertical InAs Nanowire MOSFET
(2010) 22nd International Conference on Indium Phosphide and Related Materials
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Low-frequency noise in vertical InAs nanowire FETs
- Contribution to journal › Article
-
Mark
Performance analysis of sign-based pre-FFT synchronization in OFDM systems
(2010) IEEE Vehicular Technology Conference (VTC Spring), 2010
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
