Digital ASIC-lup-obsolete
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- 2012
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Mark
Sub-VT Design of a Wake-up Receiver Back-end in 65 nm CMOS
(2012) IEEE Subthreshold Microelectronics Conference
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Re-using Chip Level DFT at Board Level
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Test Planning for Core-based 3D Stacked ICs with Through-Silicon Vias
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Selective Channelization on an SDR Platform for LTE-A Carrier Aggregation.
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Fault management in an IEEE P1687 (IJTAG) environment
(2012) 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems p.7-7
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Access Time Analysis for IEEE P1687
- Contribution to journal › Article
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Mark
Test Planning for Core-based 3D Stacked ICs under Power Constraints
(2012) IEEE International Workshop on Realiability Aware System Design and Test (RASDAT 2012)
- Contribution to conference › Paper, not in proceeding
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Mark
An MPSoCs demonstrator for fault injection and fault handling in an IEEE P1687 environment
(2012) IEEE European Test Symposium (ETS), 2012
- Contribution to conference › Paper, not in proceeding
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Mark
Integration of Full-Custom Cells in a Standard-Cell Based Flow
(2012) CDNLive! EMEA, 2012
- Contribution to conference › Paper, not in proceeding
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Mark
Area-efficient configurable high-throughput signal detector supporting multiple MIMO modes
- Contribution to journal › Article
