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- 2017
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Mark
The impact of hetero-junction and oxide-interface traps on the performance of InAs/Si and InAs/GaAsSb nanowire tunnel FETs
2017) 2017 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2017 2017-September. p.273-276(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2016
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Mark
RF Characterization of Vertical Wrap-Gated InAs/High-κ Nanowire Capacitors
(
- Contribution to journal › Article
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Mark
Ballistic modeling of InAs nanowire transistors
(
- Contribution to journal › Article
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Mark
Low Leakage-Current InAsSb Nanowire Photodetectors on Silicon.
(
- Contribution to journal › Article
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Mark
InAs/GaSb vertical nanowire TFETs on Si for digital and analogue applications
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Vertical III-V nanowire MOSFETs, TFETs, and CMOS-Gates on Si : Processing in 3D
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
High-frequency InGaAs tri-gate MOSFETs with fmax of 400 GHz
(
- Contribution to journal › Article
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Mark
InGaAs nanowire MOSFETs with ION = 555 μa/μm at IOFF = 100 nA/μm and VDD = 0.5 v
2016) 36th IEEE Symposium on VLSI Technology, VLSI Technology 2016(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
InAs nanowire GAA n-MOSFETs with 12-15 nm diameter
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Electrical Characterization and Modeling of Gate-Last Vertical InAs Nanowire MOSFETs on Si
(
- Contribution to journal › Letter