Digital ASIC-lup-obsolete
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- 2008
-
Mark
Modelling and exploration of a reconfigurable array using SystemC TLM
- Contribution to conference › Paper, not in proceeding
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Mark
A variable-rate Viterbi decoder in 130-nm CMOS: design, measurements, and cost of flexibility
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Low-Complexity Binary Morphology Architectures with Flat Rectangular Structure Elements
- Contribution to journal › Article
-
Mark
A hardware acceleration platform for digital holographic imaging
- Contribution to journal › Article
- 2007
-
Mark
Protocol Requirements in an SJTAG/IJTAG Environment
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A Heuristic for Concurrent SOC Test Scheduling with Compression and Sharing
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Extended STAPL as SJTAG Engine
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Combined Test Data Selection and Scheduling for Test Quality Optimization under ATE Memory Depth Constraint
(2007) p.221-244
- Chapter in Book/Report/Conference proceeding › Book chapter
-
Mark
Test Quality Analysis and Improvement for an Embedded Asynchronous FIFO
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Protocol Requirements in an SJTAG/IJTAG Environment
(2007) Nordic Test Forum NTF,2007
- Contribution to conference › Paper, not in proceeding
