Erik Larsson
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- 2012
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Mark
Accessing Embedded DfT Instruments with IEEE P1687
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Reusing and Retargeting On-Chip Instrument Access Procedures in IEEE P1687
(
- Contribution to journal › Article
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Mark
Scheduling Tests for 3D Stacked Chips under Power Constraints
(
- Contribution to journal › Article
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Mark
Fault management in an IEEE P1687 (IJTAG) environment
2012) 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems p.7-7(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Access Time Analysis for IEEE P1687
(
- Contribution to journal › Article
-
Mark
Test Planning for Core-based 3D Stacked ICs under Power Constraints
2012) IEEE International Workshop on Realiability Aware System Design and Test (RASDAT 2012)(
- Contribution to conference › Paper, not in proceeding
-
Mark
Re-using Chip Level DFT at Board Level
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Test Planning for Core-based 3D Stacked ICs with Through-Silicon Vias
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
An MPSoCs demonstrator for fault injection and fault handling in an IEEE P1687 environment
2012) IEEE European Test Symposium (ETS), 2012(
- Contribution to conference › Paper, not in proceeding
-
Mark
The MCNP Monte Carlo Program
2012) p.153-172(
- Chapter in Book/Report/Conference proceeding › Book chapter
- 2011
-
Mark
Test Scheduling in an IEEE P1687 Environment with Resource and Power Constraints
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Adaptive Execution Assistance for Multiplexed Fault-Tolerant Chip Multiprocessors
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
European Test Symposium (ETS) 2011
(
- Contribution to specialist publication or newspaper › Specialist publication article
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Mark
Design Automation for IEEE P1687
2011) Design, Automation and Test in Europe (DATE 2011),(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Measurement Point Selection for In-Operation Wear-Out Monitoring
2011) 14th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS11)(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Level of Confidence Evaluation and Its Usage for Roll-back Recovery with Checkpointing Optimization
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Scheduling Tests for 3D Stacked Chips under Power Constraints
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Study on the Level of Confidence for Roll-back Recovery with Checkpointing
2011) 1st Intl. Workshop on Dependability Issues in Deep-submicron Technologies (DDT 2011)(
- Contribution to conference › Paper, not in proceeding
-
Mark
A Study of Instrument Reuse and Retargeting in P1687
2011) IEEE Twelfth Workshop on RTL and High Level Testing (WRTLT 2011)(
- Contribution to conference › Paper, not in proceeding
-
Mark
SoC-Level Fault Management based on P1687 IJTAG
2011)(
- Other contribution › Miscellaneous
-
Mark
Test Planning for 3D Stacked ICs with Through-Silicon Vias
2011) Second IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits(
- Contribution to conference › Paper, not in proceeding
-
Mark
Test Scheduling for 3D Stacked ICs under Power Constraints
2011) 2nd IEEE International Workshop on Reliability Aware System Design and Test (RASDAT)(
- Contribution to conference › Paper, not in proceeding
-
Mark
Test Cost Modeling for 3D Stacked Chips with Through-Silicon Vias
2011) Swedish System-on-Chip Conference, SSoCC 2011(
- Contribution to conference › Paper, not in proceeding
-
Mark
Test Scheduling and Test Access Optimization for Core-Based 3D Stacked ICs with Through-Silicon Vias: poster
2011) IEEE European Test Symposium (ETS), 2011(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2010
-
Mark
A Distributed Architecture to Check Global Properties for Post-Silicon Debug
2010) IEEE European Test Symposium (ETS'10), 2010(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Scheduling Tests for Stacked 3D Chips under Power Constraints
2010) Swedish SoC Conference 2010(
- Contribution to conference › Paper, not in proceeding
-
Mark
Test Time Analysis for IEEE P1687
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Efficient Embedding of Deterministic Test Data
2010) 19th IEEE Asian Test Symposium (ATS10)(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Energy-Efficient Fault Tolerance in Chip Multiprocessors Using Critical Value Forwarding
2010) The 40th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN'10)Chicago, Illinois, USA, June 28-July 1, 2010. p.121-130(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Multiplexed redundant execution: A technique for efficient fault tolerance in chip multiprocessors
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Thermal Aware Test Scheduling for Stacked Multi-Chip-Modules
2010) IEEE East-West Design and Test Symposium (EWDTS10)(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Graph Theoretic Approach for Scan Cell Reordering to Minimize Peak Shift Power
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Energy-Efficient Redundant Execution for Chip Multiprocessors
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Study on Combined Test-Data Compression and Test Planning for Testing of Modular SoCs
2010)(
- Chapter in Book/Report/Conference proceeding › Book chapter
-
Mark
Optimizing Fault Tolerance for Multi-Processor System-on-Chip
2010)(
- Chapter in Book/Report/Conference proceeding › Book chapter
-
Mark
Mapping and Scheduling of Jobs in Homogeneous NoC-based MPSoC
2010) Swedish SoC Conference 2010(
- Contribution to conference › Paper, not in proceeding
-
Mark
Test Scheduling of Modular System-on-Chip under Capture Power Constraint
2010) IEEE Eleventh Workshop on RTL and High Level Testing, 2010(
- Contribution to conference › Paper, not in proceeding
-
Mark
Checking Pipelined Distributed and Global Properties at Post-silicon Debug
2010) DAC Workshop on Diagnostic Services in Network-on-Chips (DSNoC'10)(
- Contribution to conference › Paper, not in proceeding
-
Mark
Estimating Error-Probability and Its Application for Optimizing Roll-back Recovery with Checkpointing
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Test scheduling on IJTAG
2010) Nordic Test Forum (NTF 2010),(
- Contribution to conference › Paper, not in proceeding
-
Mark
Scan Cells Reordering to Minimize Peak Power During Test Cycle : A Graph Theoretic Approach
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
On-line Techniques to Adjust and Optimize Checkpointing Frequency
2010) IEEE International Workshop on Realiability Aware System Design and Test (RASDAT 2010) p.29-33(
- Contribution to conference › Paper, not in proceeding
-
Mark
Efficient Embedding of Deterministic Test Data
2010) Swedish SoC Conference 2010(
- Contribution to conference › Paper, not in proceeding
-
Mark
Checking Pipelined Distributed Global Properties for Post-silicon Debug
2010) IEEE Eleventh Workshop on RTL and High Level Testing, 2010(
- Contribution to conference › Paper, not in proceeding
-
Mark
Power Constrained Test Scheduling for 3D Stacked Chips: poster
2010) 1st IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits(
- Contribution to conference › Poster
- 2009
-
Mark
Power-Aware System-Level DfT and Test Planning
2009)(
- Chapter in Book/Report/Conference proceeding › Book chapter
-
Mark
Scan Cell Reordering to Minimize Peak Power during Scan Testing of SoC
(
- Contribution to conference › Paper, not in proceeding
-
Mark
An Even-Odd DFD Technique for Scan Chain Diagnosis
2009) Workshop on RTL and High Level Testing (WRTLT)(
- Contribution to conference › Paper, not in proceeding
-
Mark
Deterministic Scan-Chain Diagnosis for Intermittent Faults
2009) European Test Symposium, ETS 2009(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
On Minimization of Peak Power for Scan Circuit during Test
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding