Erik Larsson
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- 2009
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Mark
Fault-tolerant average execution time optimization for general-purpose multi-processor system-on-chips
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Fault-Tolerant Average Execution Time Optimization for System-On-Chips
2009) Frontiers of High Performance Embedded Computing(
- Contribution to conference › Paper, not in proceeding
-
Mark
Power Efficient Redundant Execution for Chip Multiprocessors
(
- Contribution to conference › Paper, not in proceeding
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Mark
Generation of Minimal Leakage Input Vectors with Constrained NBTI Degradation
(
- Contribution to conference › Paper, not in proceeding
-
Mark
Thermal Aware Test Scheduling for Stacked Multi-Chip-Modules
2009) DATE 2009 Friday Workshop on 3D Integration - Technology, Architecture, Design, Automation, and Tes(
- Contribution to conference › Paper, not in proceeding
-
Mark
On Scan Chain Diagnosis for Intermittent Faults
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Capture Power Reduction for Modular System-on-Chip Test
2009) IEEE/VSI VLSI Design and Test Symposium (VDAT)(
- Contribution to conference › Paper, not in proceeding
- 2008
-
Mark
Test-Architecture Optimization and Test Scheduling for SOCs with Core-Level Expansion of Compressed Test Patterns
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Cycle-Accurate Test Power Modeling and its Application to SoC Test Architecture Design and Scheduling
2008) In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 27(5). p.973-977(
- Contribution to journal › Article
-
Mark
An Architecture for Integrated Test Data Compression and Abort-on-Fail Testing in a Multi-Site Environment
(
- Contribution to journal › Article
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Mark
Core-Level Expansion of Compressed Test Patterns
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
An Integrated System-on-Chip Test Framework
2008) p.439-454(
- Chapter in Book/Report/Conference proceeding › Book chapter
-
Mark
A reconfigurable power conscious core wrapper and its application to system-on-chip test scheduling
(
- Contribution to journal › Article
-
Mark
SOC Test Optimization with Compression-Technique Selection
2008) A Workshop in Conjunction with the International Test Conference(
- Contribution to conference › Paper, not in proceeding
-
Mark
Test Response Compression for Diagnosis in Volume Production
2008) DAC08 Workshop on Diagnostic Services in Network-on-Chips DSNOC(
- Contribution to conference › Paper, not in proceeding
-
Mark
On Reduction of Capture Power for Modular System-on-Chip Test
2008) IEEE Workshop on RTL and High Level Testing WRTLT08(
- Contribution to conference › Paper, not in proceeding
- 2007
-
Mark
Extended STAPL as SJTAG Engine
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
What Impacts Course Evaluation?
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Test Data Truncation for Test Quality Maximization under ATE Memory Depth Constraint
(
- Contribution to journal › Article
-
Mark
An Architecture for Combined Test Data Compression and Abort-on-Fail Test
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A Heuristic for Concurrent SOC Test Scheduling with Compression and Sharing
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Improved Scan Chain Diagnosis
2007) 15th NXP IC Test Symposium(
- Contribution to conference › Paper, not in proceeding
-
Mark
Combined Test Data Selection and Scheduling for Test Quality Optimization under ATE Memory Depth Constraint
2007) p.221-244(
- Chapter in Book/Report/Conference proceeding › Book chapter
-
Mark
Test Quality Analysis and Improvement for an Embedded Asynchronous FIFO
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Optimized Integration of Test Compression and Sharing for SOC Testing
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Protocol Requirements in an SJTAG/IJTAG Environment
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Protocol Requirements in an SJTAG/IJTAG Environment
2007) Nordic Test Forum NTF,2007(
- Contribution to conference › Paper, not in proceeding
- 2006
-
Mark
System-on-chip test scheduling with reconfigurable core wrappers
(
- Contribution to journal › Article
-
Mark
Power-Aware Test Planning in the Early System-On-Chip Design Exploration Process
(
- Contribution to journal › Article
-
Mark
Cycle-Accurate Test Power Modeling and its Application to SoC Test Scheduling
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Combined Test Data Compression and Abort-on-Fail Test
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
High-Quality Low-Cost Test and DfT for an Embedded Asynchronous FIFO
2006) 14th Philips Research IC Test Seminar(
- Contribution to conference › Paper, not in proceeding
- 2005
-
Mark
Abort-on-Fail Based Test Scheduling
(
- Contribution to journal › Article
-
Mark
Optimization of a Bus-based Test Data Transportation Mechanism in System-on-Chip
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Test Scheduling for Modular SOCs in an Abort-on-Fail Environment
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Boundary-Scan Test Control in the ATCA Standard
2005)(
- Contribution to conference › Paper, not in proceeding
-
Mark
Introduction to Advanced System-on-Chip Test Design and Optimization
2005) In Frontiers in Electronic Testing(
- Book/Report › Book
-
Mark
SOC Test Scheduling with Test Set Sharing and Broadcasting
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Remote Boundary-Scan System Test Control for the ATCA Standard
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Multiple Constraints Driven System-on-Chip Test Time Optimization
(
- Contribution to journal › Article
-
Mark
Emerging strategies for resource-constrained testing of system chips
2005)(
- Other contribution › Miscellaneous
-
Mark
A Test Data Compression Architecture with Abort-on Fail Capability
2005) IEEE Workshop on RTL and High Level Testing WRTLT(
- Contribution to conference › Paper, not in proceeding
-
Mark
Combined Test Data Selection and Scheduling for Test Quality Optimization under ATE Memory Depth Constraint
2005) IFIP WG 10.5 Conference on Very Large Scale Integration System-on-Chip {IFIP VLSI-SOC 2005} p.429-434(
- Contribution to conference › Paper, not in proceeding
- 2004
-
Mark
An Integrated Technique for Test Vector Selection and Test Scheduling under Test Time Constraint
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Defect-Aware SOC Test Scheduling
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Core Selection Integrated in the SOC Test Solution Design-Flow
2004)(
- Other contribution › Miscellaneous
-
Mark
Integrating Core Selection in the SOC Test Solution Design-Flow
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Efficient test solutions for core-based designs
2004) In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 23(5). p.758-775(
- Contribution to journal › Article
-
Mark
A Technique for Optimization of System-on-Chip Test Data Transportation
(
- Contribution to conference › Paper, not in proceeding
-
Mark
Preemptive system-on-chip test scheduling
(
- Contribution to journal › Article