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- 2018
-
Mark
Capacitance Measurements in Vertical III-V Nanowire TFETs
(
- Contribution to journal › Letter
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Mark
A Self-aligned Gate-last Process applied to All-III-V CMOS on Si
(
- Contribution to journal › Article
-
Mark
Vertical nanowire TFETs with channel diameter down to 10 nm and point S MIN of 35 mV/decade
(
- Contribution to journal › Article
- 2017
-
Mark
Impact of Band-Tails on the Subthreshold Swing of III-V Tunnel Field-Effect Transistor
(
- Contribution to journal › Letter
-
Mark
Low-Frequency Noise in III-V Nanowire TFETs and MOSFETs
2017) In IEEE Electron Device Letters(
- Contribution to journal › Letter
- 2016
-
Mark
Electrical Characterization and Modeling of Gate-Last Vertical InAs Nanowire MOSFETs on Si
(
- Contribution to journal › Letter
-
Mark
3-D Integrated Track-and-Hold Circuit Using InAs Nanowire MOSFETs and Capacitors
(
- Contribution to journal › Article
-
Mark
High-Performance Lateral Nanowire InGaAs MOSFETs with Improved On-Current
(
- Contribution to journal › Article
-
Mark
Scaling of Vertical InAs–GaSb Nanowire Tunneling Field-Effect Transistors on Si
(
- Contribution to journal › Letter
- 2014
-
Mark
High-Frequency Gate-All-Around Vertical InAs Nanowire MOSFETs on Si Substrates
(
- Contribution to journal › Article