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- 2023
-
Mark
Effects of Interface Oxidation on Noise Properties and Performance in III–V Vertical Nanowire Memristors
(
- Contribution to journal › Article
- 2022
-
Mark
Improved Electrostatics through Digital Etch Schemes in Vertical GaSb Nanowire p-MOSFETs on Si
(
- Contribution to journal › Article
- 2021
-
Mark
Doping Profiles in Ultrathin Vertical VLS-Grown InAs Nanowire MOSFETs with High Performance
(
- Contribution to journal › Article
- 2019
-
Mark
Low-Frequency Noise in Nanowire and Planar III-V MOSFETs
2019) In Microelectronic Engineering(
- Contribution to journal › Article
- 2018
-
Mark
A Self-aligned Gate-last Process applied to All-III-V CMOS on Si
(
- Contribution to journal › Article
-
Mark
Vertical nanowire TFETs with channel diameter down to 10 nm and point S MIN of 35 mV/decade
(
- Contribution to journal › Article
-
Mark
Capacitance Measurements in Vertical III-V Nanowire TFETs
(
- Contribution to journal › Letter
- 2017
-
Mark
Low-Frequency Noise in III-V Nanowire TFETs and MOSFETs
2017) In IEEE Electron Device Letters(
- Contribution to journal › Letter
- 2016
-
Mark
Scaling of Vertical InAs–GaSb Nanowire Tunneling Field-Effect Transistors on Si
(
- Contribution to journal › Letter
- 2015
-
Mark
III-V Nanowire Complementary Metal-Oxide Semiconductor Transistors Monolithically Integrated on Si
(
- Contribution to journal › Article