1 – 10 of 11
- show: 10
- |
- sort: year (new to old)
Close
Embed this list
<iframe src=" "
width=" "
height=" "
allowtransparency="true"
frameborder="0">
</iframe>
- 2023
-
Mark
Vertical III-V Nanowire Transistors for Low-Power Electronics
2023)(
- Thesis › Doctoral thesis (compilation)
-
Mark
Low-Power, Self-Aligned Vertical InGaAsSb NW PMOS With S < 100 mV/dec
(
- Contribution to journal › Article
- 2020
-
Mark
Vertical InAs/InGaAsSb/GaSb Nanowire Tunnel FETs on Si with Drain Field-Plate and EOT = 1 nm Achieving Smin= 32 mV/dec and gm/ID= 100 V-1
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Strain mapping inside an individual processed vertical nanowire transistor using scanning X-ray nanodiffraction
(
- Contribution to journal › Article
-
Mark
Tuning of Source Material for InAs/InGaAsSb/GaSb Application-Specific Vertical Nanowire Tunnel FETs
(
- Contribution to journal › Article
- 2019
-
Mark
Reducing ambipolar off-state leakage currents in III-V vertical nanowire tunnel FETs using gate-drain underlap
(
- Contribution to journal › Article
-
Mark
Fabrication of Tunnel FETs demonstrating sub-thermal subthreshold slope
2019) 21th International Vacuum Congress(
- Contribution to conference › Abstract
- 2018
-
Mark
Capacitance Measurements in Vertical III-V Nanowire TFETs
(
- Contribution to journal › Letter
-
Mark
RF Characterisation of Vertical III-V Nanowire Tunnel FETs
2018) Swedish Microwave Days 2018(
- Contribution to conference › Paper, not in proceeding
-
Mark
Effect of Gate Oxide Defects on Tunnel Transistor RF Performance
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding