Lars-Erik Wernersson
21 – 30 of 352
- show: 10
- |
- sort: year (new to old)
Close
Embed this list
<iframe src=""
width=""
height=""
allowtransparency="true"
frameborder="0">
</iframe>
- 2023
-
Mark
Reconfigurable signal modulation in a ferroelectric tunnel field-effect transistor
- Contribution to journal › Article
-
Mark
Low-Power, Self-Aligned Vertical InGaAsSb NW PMOS With S < 100 mV/dec
- Contribution to journal › Article
-
Mark
Effects of Interface Oxidation on Noise Properties and Performance in III–V Vertical Nanowire Memristors
- Contribution to journal › Article
-
Mark
Geometric control of diffusing elements on InAs semiconductor surfaces via metal contacts
- Contribution to journal › Article
- 2022
-
Mark
A 4F2 Vertical Gate-all-around Nanowire Compute-in-memory Device Integrated in (1T1R) Cross-Point Arrays on Silicon
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Directed Self‐Assembly for Dense Vertical III–V Nanowires on Si and Implications for Gate All‐Around Deposition
- Contribution to journal › Article
-
Mark
Performance enhancement of GaSb vertical nanowire p-type MOSFETs on Si by rapid thermal annealing
- Contribution to journal › Article
-
Mark
Performance, Analysis, and Modeling of III-V Vertical Nanowire MOSFETs on Si at Higher Voltages
- Contribution to journal › Article
-
Mark
Integration of Ferroelectric HfxZr1-xO2 on Vertical III-V Nanowire Gate-All-Around FETs on Silicon
- Contribution to journal › Article
-
Mark
Improved Electrostatics through Digital Etch Schemes in Vertical GaSb Nanowire p-MOSFETs on Si
- Contribution to journal › Article
