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- 2023
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Mark
Effects of Interface Oxidation on Noise Properties and Performance in III–V Vertical Nanowire Memristors
(
- Contribution to journal › Article
- 2022
-
Mark
Improved Electrostatics through Digital Etch Schemes in Vertical GaSb Nanowire p-MOSFETs on Si
(
- Contribution to journal › Article
- 2021
-
Mark
Doping Profiles in Ultrathin Vertical VLS-Grown InAs Nanowire MOSFETs with High Performance
(
- Contribution to journal › Article
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Mark
High-density logic-in-memory devices using vertical indium arsenide nanowires on silicon
(
- Contribution to journal › Article
-
Mark
Increased Breakdown Voltage in Vertical Heterostructure III-V Nanowire MOSFETs with a Field Plate
(
- Contribution to journal › Article
- 2020
-
Mark
Nanowire Tunnel FET with Simultaneously Reduced Subthermionic Subthreshold Swing and Off-Current due to Negative Capacitance and Voltage Pinning Effects
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- Contribution to journal › Article
-
Mark
High-Performance Vertical III-V Nanowire MOSFETs on Si with gm> 3 mS/μm
(
- Contribution to journal › Article
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Mark
Tuning of Source Material for InAs/InGaAsSb/GaSb Application-Specific Vertical Nanowire Tunnel FETs
(
- Contribution to journal › Article
- 2019
-
Mark
Electrical Properties of Vertical InAs/InGaAs Heterostructure MOSFETs
(
- Contribution to journal › Article
- 2018
-
Mark
A Self-aligned Gate-last Process applied to All-III-V CMOS on Si
(
- Contribution to journal › Article