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- 2022
-
Mark
Improved Electrostatics through Digital Etch Schemes in Vertical GaSb Nanowire p-MOSFETs on Si
(
- Contribution to journal › Article
-
Mark
Low-Frequency Noise in Vertical InAs/InGaAs Gate-All-Around MOSFETs at 15 K for Cryogenic Applications
(
- Contribution to journal › Article
- 2021
-
Mark
Doping Profiles in Ultrathin Vertical VLS-Grown InAs Nanowire MOSFETs with High Performance
(
- Contribution to journal › Article
-
Mark
Increased Breakdown Voltage in Vertical Heterostructure III-V Nanowire MOSFETs with a Field Plate
(
- Contribution to journal › Article
- 2020
-
Mark
High-Performance Vertical III-V Nanowire MOSFETs on Si with gm> 3 mS/μm
(
- Contribution to journal › Article
- 2019
-
Mark
Balanced Drive Currents in 10–20 nm Diameter Nanowire All-III-V CMOS on Si
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Electrical Properties of Vertical InAs/InGaAs Heterostructure MOSFETs
(
- Contribution to journal › Article
-
Mark
Low-Frequency Noise in Nanowire and Planar III-V MOSFETs
2019) In Microelectronic Engineering(
- Contribution to journal › Article
- 2018
-
Mark
A Self-aligned Gate-last Process applied to All-III-V CMOS on Si
(
- Contribution to journal › Article
- 2017
-
Mark
Low-Frequency Noise in III-V Nanowire TFETs and MOSFETs
2017) In IEEE Electron Device Letters(
- Contribution to journal › Letter