Lars-Erik Wernersson
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- 2020
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Mark
Reduced annealing temperature for ferroelectric HZO on InAs with enhanced polarization
- Contribution to journal › Article
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Mark
Feature size control using surface reconstruction temperature in block copolymer lithography for InAs nanowire growth
- Contribution to journal › Article
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Mark
Nanowire Tunnel FET with Simultaneously Reduced Subthermionic Subthreshold Swing and Off-Current due to Negative Capacitance and Voltage Pinning Effects
- Contribution to journal › Article
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Mark
A method for estimating defects in ferroelectric thin film MOSCAPs
- Contribution to journal › Article
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Mark
III-V Nanowire MOSFETs : RF-Properties and Applications
(2020) 2020 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, BCICTS 2020
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Low-Power Resistive Memory Integrated on III-V Vertical Nanowire MOSFETs on Silicon
- Contribution to journal › Article
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Mark
Compressively-strained GaSb nanowires with core-shell heterostructures
- Contribution to journal › Article
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Mark
Tuning of Source Material for InAs/InGaAsSb/GaSb Application-Specific Vertical Nanowire Tunnel FETs
- Contribution to journal › Article
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Mark
Vertical InAs/InGaAsSb/GaSb Nanowire Tunnel FETs on Si with Drain Field-Plate and EOT = 1 nm Achieving Smin= 32 mV/dec and gm/ID= 100 V-1
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Gate-Length Dependence of Vertical GaSb Nanowire p-MOSFETs on Si
- Contribution to journal › Article
