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- 2024
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Mark
TFET Circuit Configurations Operating below 60 mV/dec
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- Contribution to journal › Article
- 2022
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Mark
Lateral III-V Nanowire MOSFETs in Low-Noise Amplifier Stages
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- Contribution to journal › Article
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Mark
Low-Frequency Noise in Vertical InAs/InGaAs Gate-All-Around MOSFETs at 15 K for Cryogenic Applications
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- Contribution to journal › Article
- 2021
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Mark
Increased Breakdown Voltage in Vertical Heterostructure III-V Nanowire MOSFETs with a Field Plate
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- Contribution to journal › Article
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Mark
Millimeter-Wave Vertical III-V Nanowire MOSFET Device-To-Circuit Co-Design
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- Contribution to journal › Article
- 2019
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Mark
Balanced Drive Currents in 10–20 nm Diameter Nanowire All-III-V CMOS on Si
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- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Electrical Properties of Vertical InAs/InGaAs Heterostructure MOSFETs
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- Contribution to journal › Article
- 2018
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Mark
Vertical nanowire TFETs with channel diameter down to 10 nm and point S MIN of 35 mV/decade
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- Contribution to journal › Article
- 2012
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Mark
Performance Evaluation of III–V Nanowire Transistors
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- Contribution to journal › Article