Nano Electronics
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- 2020
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Mark
Tuning of Source Material for InAs/InGaAsSb/GaSb Application-Specific Vertical Nanowire Tunnel FETs
(
- Contribution to journal › Article
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Mark
Cross-Point Arrays with Low-Power ITO-HfO2 Resistive Memory Cells Integrated on Vertical III-V Nanowires
(
- Contribution to journal › Article
- 2019
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Mark
Low-Temperature Front-Side BEOL Technology with Circuit Level Multiline Thru-Reflect-Line Kit for III-V MOSFETs on Silicon
2019) 92nd ARFTG Microwave Measurement Conference, ARFTG 2019(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Trap-aware compact modeling and power-performance assessment of III-V tunnel FET
2019) 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Facet-selective group-III incorporation in InGaAs template assisted selective epitaxy
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- Contribution to journal › Article
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Mark
Vertical Gate-All-Around Nanowire GaSb-InAs Core-Shell n-Type Tunnel FETs
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- Contribution to journal › Article
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Mark
An Experimental Study of Heterostructure Tunnel FET Nanowire Arrays : Digital and Analog Figures of Merit from 300K to 10K
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- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Balanced Drive Currents in 10–20 nm Diameter Nanowire All-III-V CMOS on Si
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Electrical Properties of Vertical InAs/InGaAs Heterostructure MOSFETs
(
- Contribution to journal › Article
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Mark
Comparison of Low-Frequency Noise in Nanowire and Planar III-V MOSFETs
2019) Insulating Films on Semiconductors (INFOS)(
- Contribution to conference › Paper, not in proceeding