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- 2020
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Mark
Vertical nanowire III–V MOSFETs with improved high-frequency gain
(
- Contribution to journal › Article
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Cross-Point Arrays with Low-Power ITO-HfO2 Resistive Memory Cells Integrated on Vertical III-V Nanowires
(
- Contribution to journal › Article
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Mark
Compressively-strained GaSb nanowires with core-shell heterostructures
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- Contribution to journal › Article
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Mark
Feature size control using surface reconstruction temperature in block copolymer lithography for InAs nanowire growth
(
- Contribution to journal › Article
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Mark
Strain mapping inside an individual processed vertical nanowire transistor using scanning X-ray nanodiffraction
(
- Contribution to journal › Article
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Mark
Nanowire Tunnel FET with Simultaneously Reduced Subthermionic Subthreshold Swing and Off-Current due to Negative Capacitance and Voltage Pinning Effects
(
- Contribution to journal › Article
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Mark
Reduced annealing temperature for ferroelectric HZO on InAs with enhanced polarization
(
- Contribution to journal › Article
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Mark
A phase-correlated duo-binary waveform generation technique for millimeter-wave radar pulses
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- Contribution to journal › Article
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Mark
Low-Power Resistive Memory Integrated on III-V Vertical Nanowire MOSFETs on Silicon
(
- Contribution to journal › Article
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Mark
III-V Nanowire MOSFETs : RF-Properties and Applications
2020) 2020 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, BCICTS 2020(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding