Nano Electronics
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- 2019
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Mark
Fabrication of Tunnel FETs demonstrating sub-thermal subthreshold slope
2019) 21th International Vacuum Congress(
- Contribution to conference › Abstract
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Mark
Low-temperature back-end-of-line technology compatible with III-V nanowire MOSFETs
(
- Contribution to journal › Article
- 2018
-
Mark
Clutter analysis in a time-domain millimeter-wave reflectometry setup
2018) 12th European Conference on Antennas and Propagation, EuCAP 2018(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Impact of Non-idealities on the Performance of InAs/(In)GaAsSb/GaSb Tunnel FETs
2018) In Composants nanoélectroniques(
- Contribution to journal › Article
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Mark
Capacitance Measurements in Vertical III-V Nanowire TFETs
(
- Contribution to journal › Letter
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Mark
Sub-100-nm gate-length scaling of vertical InAs/InGaAs nanowire MOSFETs on Si
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
RF Characterisation of Vertical III-V Nanowire Tunnel FETs
2018) Swedish Microwave Days 2018(
- Contribution to conference › Paper, not in proceeding
-
Mark
Vertical nanowire TFETs with channel diameter down to 10 nm and point S MIN of 35 mV/decade
(
- Contribution to journal › Article
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Mark
Effect of Gate Oxide Defects on Tunnel Transistor RF Performance
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Impact of source doping on the performance of vertical InAs/InGaAsSb/GaSb nanowire Tunnel Field-Effect Transistors
(
- Contribution to journal › Article