Lars-Erik Wernersson
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- 2016
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Mark
Vertical III-V nanowire MOSFETs, TFETs, and CMOS-Gates on Si : Processing in 3D
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
High-Performance Lateral Nanowire InGaAs MOSFETs with Improved On-Current
(
- Contribution to journal › Article
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Mark
High-frequency InGaAs tri-gate MOSFETs with fmax of 400 GHz
(
- Contribution to journal › Article
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Mark
Electrical Characterization and Modeling of Gate-Last Vertical InAs Nanowire MOSFETs on Si
(
- Contribution to journal › Letter
-
Mark
Self-aligned, gate-last process for vertical InAs nanowire MOSFETs on Si
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
ZrO2 and HfO2 dielectrics on (001) n-InAs with atomic-layer-deposited in situ surface treatment
(
- Contribution to journal › Article
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Mark
Scaling of Vertical InAs–GaSb Nanowire Tunneling Field-Effect Transistors on Si
(
- Contribution to journal › Letter
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Mark
Single suspended InGaAs nanowire MOSFETs
(
- Contribution to journal › Article
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Mark
Amplifier Design Using Vertical InAs Nanowire MOSFETs
(
- Contribution to journal › Article
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Mark
Low Trap Density in InAs/High-k Nanowire Gate Stacks with Optimized Growth and Doping Conditions
(
- Contribution to journal › Article