Johannes Svensson
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- 2020
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Mark
Strain mapping inside an individual processed vertical nanowire transistor using scanning X-ray nanodiffraction
(
- Contribution to journal › Article
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Mark
Tuning of Source Material for InAs/InGaAsSb/GaSb Application-Specific Vertical Nanowire Tunnel FETs
(
- Contribution to journal › Article
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Mark
A method for estimating defects in ferroelectric thin film MOSCAPs
(
- Contribution to journal › Article
- 2019
-
Mark
Electrical Properties of Vertical InAs/InGaAs Heterostructure MOSFETs
(
- Contribution to journal › Article
-
Mark
Balanced Drive Currents in 10–20 nm Diameter Nanowire All-III-V CMOS on Si
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Low-Frequency Noise in Nanowire and Planar III-V MOSFETs
2019) In Microelectronic Engineering(
- Contribution to journal › Article
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Mark
Integration of InSb on Si by Rapid Melt Growth
2019) 21th International Vacuum Congress(
- Contribution to conference › Abstract
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Mark
Reducing ambipolar off-state leakage currents in III-V vertical nanowire tunnel FETs using gate-drain underlap
(
- Contribution to journal › Article
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Mark
Fabrication of Tunnel FETs demonstrating sub-thermal subthreshold slope
2019) 21th International Vacuum Congress(
- Contribution to conference › Abstract
-
Mark
Comparison of Low-Frequency Noise in Nanowire and Planar III-V MOSFETs
2019) Insulating Films on Semiconductors (INFOS)(
- Contribution to conference › Paper, not in proceeding