Lars-Erik Wernersson
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- 2021
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Mark
High-density logic-in-memory devices using vertical indium arsenide nanowires on silicon
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- Contribution to journal › Article
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Mark
Doping Profiles in Ultrathin Vertical VLS-Grown InAs Nanowire MOSFETs with High Performance
(
- Contribution to journal › Article
- 2020
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Mark
Reduced annealing temperature for ferroelectric HZO on InAs with enhanced polarization
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- Contribution to journal › Article
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Mark
A phase-correlated duo-binary waveform generation technique for millimeter-wave radar pulses
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- Contribution to journal › Article
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Mark
Nanowire Tunnel FET with Simultaneously Reduced Subthermionic Subthreshold Swing and Off-Current due to Negative Capacitance and Voltage Pinning Effects
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- Contribution to journal › Article
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Mark
Feature size control using surface reconstruction temperature in block copolymer lithography for InAs nanowire growth
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- Contribution to journal › Article
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Mark
Tuning of Source Material for InAs/InGaAsSb/GaSb Application-Specific Vertical Nanowire Tunnel FETs
(
- Contribution to journal › Article
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Mark
Vertical InAs/InGaAsSb/GaSb Nanowire Tunnel FETs on Si with Drain Field-Plate and EOT = 1 nm Achieving Smin= 32 mV/dec and gm/ID= 100 V-1
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Cross-Point Arrays with Low-Power ITO-HfO2 Resistive Memory Cells Integrated on Vertical III-V Nanowires
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- Contribution to journal › Article
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Mark
Effects of traps in the gate stack on the small-signal RF response of III-V nanowire MOSFETs
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- Contribution to journal › Article