Lars-Erik Wernersson
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- 2019
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Mark
Trap-aware compact modeling and power-performance assessment of III-V tunnel FET
2019) 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Electrical Properties of Vertical InAs/InGaAs Heterostructure MOSFETs
(
- Contribution to journal › Article
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Mark
Balanced Drive Currents in 10–20 nm Diameter Nanowire All-III-V CMOS on Si
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Millimeter-Wave Pulse Radar Scattering Measurements on the Human Hand
(
- Contribution to journal › Article
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Mark
Comparison of Low-Frequency Noise in Nanowire and Planar III-V MOSFETs
2019) Insulating Films on Semiconductors (INFOS)(
- Contribution to conference › Paper, not in proceeding
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Mark
Low-Frequency Noise in Nanowire and Planar III-V MOSFETs
2019) In Microelectronic Engineering(
- Contribution to journal › Article
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Mark
Core-shell tfet developments and tfet limitations
2019) 2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Reducing ambipolar off-state leakage currents in III-V vertical nanowire tunnel FETs using gate-drain underlap
(
- Contribution to journal › Article
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Mark
Fabrication of Tunnel FETs demonstrating sub-thermal subthreshold slope
2019) 21th International Vacuum Congress(
- Contribution to conference › Abstract
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Mark
Low-temperature back-end-of-line technology compatible with III-V nanowire MOSFETs
(
- Contribution to journal › Article