Lars-Erik Wernersson
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- 2020
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Mark
Strain mapping inside an individual processed vertical nanowire transistor using scanning X-ray nanodiffraction
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- Contribution to journal › Article
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Cross-Point Arrays with Low-Power ITO-HfO2 Resistive Memory Cells Integrated on Vertical III-V Nanowires
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- Contribution to journal › Article
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Mark
Effects of traps in the gate stack on the small-signal RF response of III-V nanowire MOSFETs
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- Contribution to journal › Article
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Vertical nanowire III–V MOSFETs with improved high-frequency gain
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- Contribution to journal › Article
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Mark
Feature size control using surface reconstruction temperature in block copolymer lithography for InAs nanowire growth
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- Contribution to journal › Article
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Mark
Compressively-strained GaSb nanowires with core-shell heterostructures
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- Contribution to journal › Article
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Mark
III-V Nanowire MOSFETs : RF-Properties and Applications
2020) 2020 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, BCICTS 2020(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
A method for estimating defects in ferroelectric thin film MOSCAPs
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- Contribution to journal › Article
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Tuning of Source Material for InAs/InGaAsSb/GaSb Application-Specific Vertical Nanowire Tunnel FETs
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- Contribution to journal › Article
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Mark
Vertical InAs/InGaAsSb/GaSb Nanowire Tunnel FETs on Si with Drain Field-Plate and EOT = 1 nm Achieving Smin= 32 mV/dec and gm/ID= 100 V-1
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- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding