Olli-Pekka Kilpi (Former)
1 – 17 of 17
- show: 250
- |
- sort: year (new to old)
Close
Embed this list
<iframe src=" "
width=" "
height=" "
allowtransparency="true"
frameborder="0">
</iframe>
- 2022
-
Mark
Performance, Analysis, and Modeling of III-V Vertical Nanowire MOSFETs on Si at Higher Voltages
(
- Contribution to journal › Article
- 2021
-
Mark
Increased Breakdown Voltage in Vertical Heterostructure III-V Nanowire MOSFETs with a Field Plate
(
- Contribution to journal › Article
- 2020
-
Mark
High-Performance Vertical III-V Nanowire MOSFETs on Si with gm> 3 mS/μm
(
- Contribution to journal › Article
-
Mark
Cross-Point Arrays with Low-Power ITO-HfO2 Resistive Memory Cells Integrated on Vertical III-V Nanowires
(
- Contribution to journal › Article
-
Mark
Effects of traps in the gate stack on the small-signal RF response of III-V nanowire MOSFETs
(
- Contribution to journal › Article
-
Mark
Vertical nanowire III–V MOSFETs with improved high-frequency gain
(
- Contribution to journal › Article
- 2019
-
Mark
Low-Frequency Noise in Nanowire and Planar III-V MOSFETs
2019) In Microelectronic Engineering(
- Contribution to journal › Article
-
Mark
Electrical Properties of Vertical InAs/InGaAs Heterostructure MOSFETs
(
- Contribution to journal › Article
-
Mark
Comparison of Low-Frequency Noise in Nanowire and Planar III-V MOSFETs
2019) Insulating Films on Semiconductors (INFOS)(
- Contribution to conference › Paper, not in proceeding
-
Mark
Low-temperature back-end-of-line technology compatible with III-V nanowire MOSFETs
(
- Contribution to journal › Article
-
Mark
Vertical III-V Nanowire MOSFETs
2019) In Series of licentiate and doctoral theses(
- Thesis › Doctoral thesis (compilation)
- 2018
-
Mark
Sub-100-nm gate-length scaling of vertical InAs/InGaAs nanowire MOSFETs on Si
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2017
-
Mark
Vertical InAs/InGaAs Heterostructure Metal-Oxide-Semiconductor Field-Effect Transistors on Si
(
- Contribution to journal › Article
-
Mark
Low-Frequency Noise in III-V Nanowire TFETs and MOSFETs
2017) In IEEE Electron Device Letters(
- Contribution to journal › Letter
-
Mark
Vertical heterojunction InAs/InGaAs nanowire MOSFETs on Si with Ion = 330 μa/μm at Ioff = 100 nA/μm and VD = 0.5 v
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2016
-
Mark
Electrical Characterization and Modeling of Gate-Last Vertical InAs Nanowire MOSFETs on Si
(
- Contribution to journal › Letter
-
Mark
Self-aligned, gate-last process for vertical InAs nanowire MOSFETs on Si
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding