Lars-Erik Wernersson
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- 2020
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Mark
Strain mapping inside an individual processed vertical nanowire transistor using scanning X-ray nanodiffraction
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- Contribution to journal › Article
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Mark
Nanowire Tunnel FET with Simultaneously Reduced Subthermionic Subthreshold Swing and Off-Current due to Negative Capacitance and Voltage Pinning Effects
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- Contribution to journal › Article
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Mark
Compressively-strained GaSb nanowires with core-shell heterostructures
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- Contribution to journal › Article
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Mark
Feature size control using surface reconstruction temperature in block copolymer lithography for InAs nanowire growth
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- Contribution to journal › Article
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Mark
A phase-correlated duo-binary waveform generation technique for millimeter-wave radar pulses
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- Contribution to journal › Article
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Mark
III-V Nanowire MOSFETs : RF-Properties and Applications
2020) 2020 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, BCICTS 2020(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
A method for estimating defects in ferroelectric thin film MOSCAPs
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- Contribution to journal › Article
- 2019
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Mark
Vertical Gate-All-Around Nanowire GaSb-InAs Core-Shell n-Type Tunnel FETs
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- Contribution to journal › Article
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Mark
Low-Temperature Front-Side BEOL Technology with Circuit Level Multiline Thru-Reflect-Line Kit for III-V MOSFETs on Silicon
2019) 92nd ARFTG Microwave Measurement Conference, ARFTG 2019(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
An Experimental Study of Heterostructure Tunnel FET Nanowire Arrays : Digital and Analog Figures of Merit from 300K to 10K
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- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding