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- 2022
-
Mark
An 88% fractional bandwidth reconfigurable power amplifier for NB-IoT and LTE-M in 22 nm CMOS FDSOI
2022) 2022 IEEE Nordic Circuits and Systems Conference (NorCAS)(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2021
-
Mark
An Energy-Efficient Near-Memory Computing Architecture for CNN Inference at Cache Level
2021) p.1-4(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
FLoPAD-GRU : A Flexible, Low Power, Accelerated DSP for Gated Recurrent Unit Neural Network
2021) 34th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, SBCCI 2021 In Proceedings - 34th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, SBCCI 2021(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A Low-Voltage 6T Dual-Port Configured SRAM with Wordline Boost in 28 nm FD-SOI
2021) 47th IEEE European Solid State Circuits Conference, ESSCIRC 2021 In ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference, Proceedings p.459-462(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2018
-
Mark
A 128 kb 7T SRAM Using a Single-Cycle Boosting Mechanism in 28 nm FD–SOI
(
- Contribution to journal › Article
- 2017
-
Mark
3.6 A 60pJ/b 300Mb/s 128×8 Massive MIMO precoder-detector in 28nm FD-SOI
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
An Area Efficient Single-Cycle xVDD Sub-Vth on-Chip Boost Scheme in 28 nm FD-SOI
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Logic filter cache for wide-VDD-range processors
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2016
-
Mark
Ultra Low Voltage Synthesizable Memories: A Trade-Off Discussion in 65nm CMOS
(
- Contribution to journal › Article
-
Mark
A continuous-time delta-sigma ADC with integrated digital background calibration
(
- Contribution to journal › Article
-
Mark
Improving practical sensitivity of energy optimized wake-up receivers : Proof of concept in 65nm CMOS
(
- Contribution to journal › Article
-
Mark
A 128 Kb Single-Bitline 8.4 fJ/Bit 90MHz at 0.3V 7T Sense-Amplifierless SRAM in 28 nm FD-SOI
2016) European Solid-State Circuits Conference (ESSCIRC). 2016(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Ultra low energy and area efficient charge pump with automatic clock controller in 65 nm CMOS
2016) 11th IEEE Asian Solid-State Circuits Conference, A-SSCC 2015(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2015
-
Mark
A New Digital Front-End for Flexible Reception in Software Defined Radio
(
- Contribution to journal › Article
-
Mark
A 128-channel discrete cosine transform-based neural signal processor for implantable neural recording microsystems
(
- Contribution to journal › Article
-
Mark
A 290mV sub-VT ASIC for Real-Time Atrial Fibrillation Detection
(
- Contribution to journal › Article
-
Mark
High Throughput Constant Envelope Pre-coder for Massive MIMO Systems
2015) IEEE International Symposium on Circuits and Systems (ISCAS), 2015(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Algorithm and Hardware Aspects of Pre-coding in Massive MIMO Systems
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Digital background calibration in continuous-time delta-sigma analog to digital converters
2015) Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A 400 mV Atrial Fibrillation Detector with 0.56 pJ/Operation in 65 nm CMOS
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2014
-
Mark
A 35 fJ/bit-access Sub-VT Memory Using a Dual-Bit Area-Optimized Standard-cell in 65 nm CMOS
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Ultra low power transceivers for wireless sensors and body area networks
2014) 8th International Symposium on Medical Information and Communication Technology (ISMICT)(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A 65 nm Single Stage 28 fJ/cycle 0.12 to 1.2V Level-Shifter
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Hardware Efficient Approximative Matrix Inversion for Linear Pre-Coding in Massive MIMO
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A 0.28-0.8 V 320 fW D-latch for Sub-VT Memories in 65 nm CMOS
2014) FTFC(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A low-complex peak-to-average power reduction scheme for OFDM based massive MIMO systems
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Lessons from Ten Years of the International Master’s Program in System-on-Chip
2014) The 10th European Workshop on Microelectronics Education (EWME 2014)(
- Contribution to conference › Paper, not in proceeding
- 2013
-
Mark
Dual-VT 4kb Sub-VT Memories with <1 pW/bit Leakage in 65 nm CMOS
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Ultra Low Energy Design Exploration of Digital Decimation Filters in 65 nm Dual-VT CMOS in the Sub-VT Domain
(
- Contribution to journal › Article
-
Mark
A 65-nm CMOS Area Optimized De-synchronization Flow for sub-V-T Designs
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Next Generation Digital Front-End for Multi-Standard Concurrent Reception
2013) NORCHIP Conference, 2013(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Approximative Matrix Inverse Computations for Very-large MIMO and Applications to Linear Pre-coding Systems
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
An Ultra-Low-Power Application-Specific Processor for Compressed Sensing
(
- Chapter in Book/Report/Conference proceeding › Book chapter
-
Mark
Two Flavors of 4kb Standard-Cell Based Subvt Memory in 65 nm CMOS
2013) Swedish System-On-Chip Conference (SSoCC), 2013(
- Contribution to conference › Paper, not in proceeding
- 2012
-
Mark
Ultra Low Power Error Correction Circuits- Technology Scaling and Sub-Vt operation
(
- Contribution to journal › Article
-
Mark
High-level energy estimation in the sub-VT domain: simulation and measurement of a cardiac event detector
(
- Contribution to journal › Article
-
Mark
A receiver architecture for devices in wireless body area networks
2012) In IEEE Journal on Emerging and Selected Topics in Circuits and Systems(
- Contribution to journal › Article
-
Mark
A 100-fJ/cycle Sub-VT Decimation Filter Chain in 65 nm CMOS
2012) IEEE International Conference on Electronics, Circuits, and Systems (ICECS), 2012(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Sizing of Dual-V-T Gates for Sub-V-T Circuits
2012) IEEE Subthreshold Microelectronics Conference (SubVT)(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Sub-VT Design of a Wake-up Receiver Back-end in 65 nm CMOS
2012) IEEE Subthreshold Microelectronics Conference(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
IR-Drop Reduction in Sub-VT Circuits by De-synchronization
2012) IEEE Subthreshold Microelectronics Conference, IEEE-Sub-Vt 2012(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
TamaRISC-CS: An Ultra-Low-Power Application-Specific Processor for Compressed Sensing
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A 500 fW/bit 14 fJ/bit-access 4kb Standard-Cell Based Sub-VT Memory in 65nm CMOS
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
När blir man "självständig" forskare vid LTH?
(
- Contribution to journal › Article
-
Mark
Integration of Full-Custom Cells in a Standard-Cell Based Flow
2012) CDNLive! EMEA, 2012(
- Contribution to conference › Paper, not in proceeding
- 2011
-
Mark
Highly Scalable Implementation of a Robust MMSE Channel Estimator for OFDM Multi-Standard Environment
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Reconfigurable cell array for concurrent support of multiple radio standards by flexible mapping
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Design exploration of a 65 nm Sub-VT CMOS digital decimation filter chain
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Energy-minimum sub-threshold self-timed circuits using current sensing completion detection
2011) 16th IEEE International Symposium on Asynchronous Circuits and Systems In IET Computers and Digital Techniques 5(4). p.342-353(
- Contribution to journal › Article
-
Mark
Benchmarking of Standard-Cell Based Memories in the sub-VT Domain in 65-nm CMOS Technology
(
- Contribution to journal › Article
-
Mark
Developing independence as young academics at LTH
2011)(
- Other contribution › Miscellaneous
-
Mark
Synthesis Strategies for Sub-VT Systems
2011) 20th European Conference on Circuit Theory and Design. ECCTD 2011(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Physical implementation of analog circuits assisted by conventional digital place and route methods
2011) CDNLive! EMEA, 2011(
- Contribution to conference › Other
-
Mark
Low Power and Area Efficient Implementation of a Real-Time AF Detection Algorithm in 130 nm CMOS
2011) Swedish System-on-Chip Conference, SSoCC 2011(
- Contribution to conference › Paper, not in proceeding
-
Mark
Impact of switching activity on the energy minimum voltage for 65 nm Sub-VT CMOS
2011) 29th Norchip conference, 2011(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A GALS ASIC implementation from a CAL dataflow description
2011) 29th Norchip conference, 2011(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2010
-
Mark
Hardware Implementation of an Iterative Sampling Rate Converter for Wireless Communication
2010) IEEE Global Telecommunications Conference GLOBECOM 2010(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Energy dissipation reduction of a cardiac event detector in the sub-Vt domain by architectural folding
2010) 19th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) 2009 5953. p.347-356(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Design and Measurement of a Variable-Rate Viterbi Decoder in 130-nm Digital CMOS
(
- Contribution to journal › Article
-
Mark
Minimum-energy sub-threshold self-timed circuits: design methodology and a case study
2010) The 16th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Ultra low energy vs throughput design exploration of 65 nm sub-VT CMOS digital filters
2010) NORCHIP Conference, 2010(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Reconfigurable cell array as enabler for supporting concurrent multiple standards in mobile terminals
2010) Swedish System-on-Chip Conference 2010 (SSoCC'10)(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A sign-bit auto-correlation architecture for fractional frequency offset estimation in OFDM
(
- Contribution to conference › Paper, not in proceeding
-
Mark
Power consumption in digital filter architectures in 65 nm CMOS technology
2010) GigaHertz Symposium, 2010(
- Contribution to conference › Paper, not in proceeding
-
Mark
Energy efficiency in Sub-VT of various 16-bit adder structures in 65 nm CMOS
2010) Swedish System-on-Chip Conference 2010 (SSoCC'10)(
- Contribution to conference › Paper, not in proceeding
- 2009
-
Mark
Energy efficient biomedical signal processing in implantable devices
2009) Invited paper to the International Conference Smart Materials, Structures and Systems (CIMTEC) p.195-203(
- Contribution to conference › Paper, not in proceeding
-
Mark
A study on leakage minimization by RBB in 65 nm CMOS
2009) Swedish System-on-Chip Conference 2009 (SSoCC'09)(
- Contribution to conference › Paper, not in proceeding
-
Mark
Sign-Bit based architecture for OFDM acquisition for multiple-standards
2009) Norchip Conference, 2009(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2008
-
Mark
A variable-rate Viterbi decoder in 130-nm CMOS: design, measurements, and cost of flexibility
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2006
-
Mark
Leakage Minimization in Cardiac Rhythm Management Devices by Time-multiplexing
2006) IEEE Biomedical Circuits and Systems Conference (BIOCAS)(
- Contribution to conference › Paper, not in proceeding
- 2005
-
Mark
Digital implementation of a wavelet-based event detector for cardiac pacemakers
2005) In IEEE Transactions on Circuits and Systems Part 1: Fundamental Theory and Applications 52(12). p.2686-2698(
- Contribution to journal › Article
-
Mark
A manual on ASIC front to back end design flow
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Teaching digital ASIC design to students with heterogeneoms previous knowledge
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Development and Implementation of Cardiac Event Detectors in Digital CMOS
2005)(
- Thesis › Doctoral thesis (compilation)
-
Mark
A dual-mode wavelet based R-wave detector using single-Vt for leakage reduction [cardiac pacemaker applications]
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2004
-
Mark
A wavelet based R-wave detector for cardiac pacemakers in 0.35 CMOS technology
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A flexible wavelet filter structure for cardiac pacemakers: a power efficient implementation
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2002
-
Mark
R-wave detection for pacemakers using a matched filter based on an artificial neural network
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2001
-
Mark
QRS detection for pacemakers in a noisy environment using a time lagged artificial neural network
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding