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- 2024
-
Mark
On Modeling and Detecting Trojans in Instruction Sets
(
- Contribution to journal › Article
-
Mark
Embedded Tutorial: Access to On-chip Instruments via Functional Ports
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2023
-
Mark
Secure reuse of DfT during operation
2023) Nordic Test Forum(
- Contribution to conference › Paper, not in proceeding
-
Mark
Co-optimization of security and accessibility to on-chip instruments
2023) 24th IEEE Latin-American Test Symposium, LATS 2023(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2022
-
Mark
Reusing IEEE 1687-Compatible Instruments and Sub-Networks over a System Bus
2022) p.219-228(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Graceful degradation to prolong lifetime of semiconductors
2022) Knowledge for Sustainable Development(
– Lund University Research Conference- Contribution to conference › Poster
- 2021
-
Mark
Access to on-chip test structures via functional buses
2021) Nordic Test Forum(
- Contribution to conference › Other
-
Mark
System-Level Access to On-Chip Instruments
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Graceful Degradation of Reconfigurable Scan Networks
(
- Contribution to journal › Scientific review
-
Mark
Accessing general IEEE Std. 1687 networks via functional ports
2021) p.354-363(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2020
-
Mark
INTERNET OF THINGS AS A COMPLEMENT TO INCREASE SAFETY
(
- Contribution to journal › Article
-
Mark
IEEE Std. P1687.1 for Access Control of Reconfigurable Scan Networks
2020) 25th IEEE European Test Symposium (ETS), 2020(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Enabling Image Recognition on Constrained Devices Using Neural Network Pruning and a CycleGAN
2020) First international workshop on Internet of Things for Emergency Management (IoT4Emergency)(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2019
-
Mark
IEEE Std. P1687.1: Access to IEEE Std. 1687 via UART
2019) 4th International Test Standards Application Workshop(
- Contribution to conference › Paper, not in proceeding
-
Mark
Functional port for accessing on-chip instruments
2019) Nordic Test Forum, 2019(
- Contribution to conference › Paper, not in proceeding
-
Mark
Maintainability of large-scale IoT
2019) DTU High Tech Summit(
- Contribution to conference › Paper, not in proceeding
-
Mark
Test Flow Selection for Stacked Integrated Circuits
(
- Contribution to journal › Article
-
Mark
IEEE Std. P1687.1: translator and protocol
2019) International Test Conference (ITC)(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2018
-
Mark
Systemkretsar ställer nya krav på testningen
(
- Contribution to specialist publication or newspaper › Newspaper article
-
Mark
Test of Reconfigurable Modules in Scan Networks
(
- Contribution to journal › Article
-
Mark
On-Chip Fault Monitoring Using Self-Reconfiguring IEEE 1687 Networks
(
- Contribution to journal › Article
- 2017
-
Mark
Test Planning for Core-based Integrated Circuits under Power Constraints
(
- Contribution to journal › Article
-
Mark
Clustered checkpointing: Maximizing the level of confidence for non-equidistant checkpointing
(
- Contribution to journal › Article
-
Mark
BASTION: Board and SoC test instrumentation for ageing and no failure found
2017) In Proceedings (Design, Automation, and Test in Europe Conference and Exhibition. Online) p.115-120(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Fault Extraction in Self-Reconfiguring IEEE 1687 Networks
2017) 2nd Test Standards Application Workshop(
- Contribution to conference › Paper, not in proceeding
-
Mark
Reducing Pessimism in Upper-Bound Computation for Optimal IEEE 1687 Retargeting
2017) 2nd Test Standards Application Workshop(
- Contribution to conference › Paper, not in proceeding
- 2016
-
Mark
Optimizing the Level of Confidence for Multiple Jobs
2016) In IEEE Transactions on Computers(
- Contribution to journal › Article
-
Mark
Towards a Suite of IEEE 1687 Benchmark Networks
2016) Test Standards Application Workshop (TESTA)(
- Contribution to conference › Paper, not in proceeding
-
Mark
Retargeting Challenges in IEEE 1687 Networks
2016) Test Standards Application Workshop (TESTA)(
- Contribution to conference › Paper, not in proceeding
-
Mark
Test, Validation and Diagnosis of IEEE 1687 Networks
2016) Test Standards Application Workshop (TESTA)(
- Contribution to conference › Paper, not in proceeding
-
Mark
Automatic generation of stimuli for fault diagnosis in IEEE 1687 networks
2016) 22nd IEEE International Symposium on On-Line Testing and Robust System Design, IOLTS 2016 p.167-172(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
In-Field System-Health Monitoring Based on IEEE 1687
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
On the diagnostic analysis of IEEE 1687 networks
2016) 21st IEEE European Test Symposium, ETS 2016(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Compressor design for silicon debug
2016) 21st IEEE European Test Symposium, ETS 2016(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Accessing On-chip Instruments Through the Life-time of Systems
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A Self-Reconfiguring IEEE 1687 Network for Fault Monitoring
2016) European Test Symposium (ETS), 2016(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Upper-bound computation for optimal retargeting in IEEE1687 networks
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
On the Testability of IEEE 1687 Networks
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Maximizing level of confidence for non-equidistant Checkpointing
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Maximizing Level of Confidence for Non-Equidistant Checkpointing
2016) 21st Asia and South Pacific Design Automation Conference ASP-DAC(
- Contribution to conference › Paper, not in proceeding
- 2015
-
Mark
Abort-on-Fail Test Scheduling for Modular SOCs without and with Preemption
(
- Contribution to journal › Article
-
Mark
No Fault Found: The Root Cause
2015) IEEE VLSI Test Symposium(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Access Time Minimization in IEEE 1687 Networks
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2014
-
Mark
Design, Verification and Application of IEEE 1687
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Evaluation of Level of Confidence and Optimization of Roll-back Recovery with Checkpointing for Real-Time Systems
(
- Contribution to journal › Article
-
Mark
Test Planning and Test Access Mechanism Design for Stacked Chips using ILP
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Test Planning and Test Access Mechanism Design for 3D SICs
2014) Swedish System on Chip Conference (SSoCC), 2014(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Fault injection and fault handling: an MPSoC demonstrator using IEEE P1687
2014) 20th IEEE International On-Line Testing Symposium(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Robustness of TAP-based Scan Networks
2014) IEEE International Test Conference, 2014(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2013
-
Mark
Embedded DfT Instrumentation: Design, Access, Retargeting and Case Studies
2013) VLSI Test Symposium (VTS)(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Test Planning for 3D SICs using ILP
2013) Swedish System-On-Chip Conference (SSoCC), 2013(
- Contribution to conference › Paper, not in proceeding
-
Mark
Scenario-Based Network Design for P1687
2013) Swedish System-On-Chip Conference (SSoCC), 2013(
- Contribution to conference › Paper, not in proceeding
- 2012
-
Mark
Accessing Embedded DfT Instruments with IEEE P1687
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Reusing and Retargeting On-Chip Instrument Access Procedures in IEEE P1687
(
- Contribution to journal › Article
-
Mark
Test Planning for Core-based 3D Stacked ICs with Through-Silicon Vias
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Fault management in an IEEE P1687 (IJTAG) environment
2012) 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems p.7-7(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Re-using Chip Level DFT at Board Level
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Access Time Analysis for IEEE P1687
(
- Contribution to journal › Article
-
Mark
An MPSoCs demonstrator for fault injection and fault handling in an IEEE P1687 environment
2012) IEEE European Test Symposium (ETS), 2012(
- Contribution to conference › Paper, not in proceeding
-
Mark
Test Planning for Core-based 3D Stacked ICs under Power Constraints
2012) IEEE International Workshop on Realiability Aware System Design and Test (RASDAT 2012)(
- Contribution to conference › Paper, not in proceeding
-
Mark
The MCNP Monte Carlo Program
2012) p.153-172(
- Chapter in Book/Report/Conference proceeding › Book chapter
-
Mark
Scheduling Tests for 3D Stacked Chips under Power Constraints
(
- Contribution to journal › Article
- 2011
-
Mark
Adaptive Execution Assistance for Multiplexed Fault-Tolerant Chip Multiprocessors
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
European Test Symposium (ETS) 2011
(
- Contribution to specialist publication or newspaper › Specialist publication article
-
Mark
Test Scheduling in an IEEE P1687 Environment with Resource and Power Constraints
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Scheduling Tests for 3D Stacked Chips under Power Constraints
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Design Automation for IEEE P1687
2011) Design, Automation and Test in Europe (DATE 2011),(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Measurement Point Selection for In-Operation Wear-Out Monitoring
2011) 14th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS11)(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Level of Confidence Evaluation and Its Usage for Roll-back Recovery with Checkpointing Optimization
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Test Scheduling for 3D Stacked ICs under Power Constraints
2011) 2nd IEEE International Workshop on Reliability Aware System Design and Test (RASDAT)(
- Contribution to conference › Paper, not in proceeding
-
Mark
Study on the Level of Confidence for Roll-back Recovery with Checkpointing
2011) 1st Intl. Workshop on Dependability Issues in Deep-submicron Technologies (DDT 2011)(
- Contribution to conference › Paper, not in proceeding
-
Mark
A Study of Instrument Reuse and Retargeting in P1687
2011) IEEE Twelfth Workshop on RTL and High Level Testing (WRTLT 2011)(
- Contribution to conference › Paper, not in proceeding
-
Mark
Test Cost Modeling for 3D Stacked Chips with Through-Silicon Vias
2011) Swedish System-on-Chip Conference, SSoCC 2011(
- Contribution to conference › Paper, not in proceeding
-
Mark
Test Planning for 3D Stacked ICs with Through-Silicon Vias
2011) Second IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits(
- Contribution to conference › Paper, not in proceeding
-
Mark
SoC-Level Fault Management based on P1687 IJTAG
2011)(
- Other contribution › Miscellaneous
-
Mark
Test Scheduling and Test Access Optimization for Core-Based 3D Stacked ICs with Through-Silicon Vias: poster
2011) IEEE European Test Symposium (ETS), 2011(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2010
-
Mark
Test Time Analysis for IEEE P1687
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Efficient Embedding of Deterministic Test Data
2010) 19th IEEE Asian Test Symposium (ATS10)(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Energy-Efficient Fault Tolerance in Chip Multiprocessors Using Critical Value Forwarding
2010) The 40th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN'10)Chicago, Illinois, USA, June 28-July 1, 2010. p.121-130(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Multiplexed redundant execution: A technique for efficient fault tolerance in chip multiprocessors
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Thermal Aware Test Scheduling for Stacked Multi-Chip-Modules
2010) IEEE East-West Design and Test Symposium (EWDTS10)(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Graph Theoretic Approach for Scan Cell Reordering to Minimize Peak Shift Power
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Energy-Efficient Redundant Execution for Chip Multiprocessors
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Optimizing Fault Tolerance for Multi-Processor System-on-Chip
2010)(
- Chapter in Book/Report/Conference proceeding › Book chapter
-
Mark
A Distributed Architecture to Check Global Properties for Post-Silicon Debug
2010) IEEE European Test Symposium (ETS'10), 2010(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Study on Combined Test-Data Compression and Test Planning for Testing of Modular SoCs
2010)(
- Chapter in Book/Report/Conference proceeding › Book chapter
-
Mark
Estimating Error-Probability and Its Application for Optimizing Roll-back Recovery with Checkpointing
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Scheduling Tests for Stacked 3D Chips under Power Constraints
2010) Swedish SoC Conference 2010(
- Contribution to conference › Paper, not in proceeding
-
Mark
Mapping and Scheduling of Jobs in Homogeneous NoC-based MPSoC
2010) Swedish SoC Conference 2010(
- Contribution to conference › Paper, not in proceeding
-
Mark
Test Scheduling of Modular System-on-Chip under Capture Power Constraint
2010) IEEE Eleventh Workshop on RTL and High Level Testing, 2010(
- Contribution to conference › Paper, not in proceeding
-
Mark
Checking Pipelined Distributed and Global Properties at Post-silicon Debug
2010) DAC Workshop on Diagnostic Services in Network-on-Chips (DSNoC'10)(
- Contribution to conference › Paper, not in proceeding
-
Mark
Efficient Embedding of Deterministic Test Data
2010) Swedish SoC Conference 2010(
- Contribution to conference › Paper, not in proceeding
-
Mark
Checking Pipelined Distributed Global Properties for Post-silicon Debug
2010) IEEE Eleventh Workshop on RTL and High Level Testing, 2010(
- Contribution to conference › Paper, not in proceeding
-
Mark
Test scheduling on IJTAG
2010) Nordic Test Forum (NTF 2010),(
- Contribution to conference › Paper, not in proceeding
-
Mark
Scan Cells Reordering to Minimize Peak Power During Test Cycle : A Graph Theoretic Approach
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
On-line Techniques to Adjust and Optimize Checkpointing Frequency
2010) IEEE International Workshop on Realiability Aware System Design and Test (RASDAT 2010) p.29-33(
- Contribution to conference › Paper, not in proceeding
-
Mark
Power Constrained Test Scheduling for 3D Stacked Chips: poster
2010) 1st IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits(
- Contribution to conference › Poster
- 2009
-
Mark
Deterministic Scan-Chain Diagnosis for Intermittent Faults
2009) European Test Symposium, ETS 2009(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
On Minimization of Peak Power for Scan Circuit during Test
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Fault-tolerant average execution time optimization for general-purpose multi-processor system-on-chips
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Power-Aware System-Level DfT and Test Planning
2009)(
- Chapter in Book/Report/Conference proceeding › Book chapter
-
Mark
An Even-Odd DFD Technique for Scan Chain Diagnosis
2009) Workshop on RTL and High Level Testing (WRTLT)(
- Contribution to conference › Paper, not in proceeding
-
Mark
Scan Cell Reordering to Minimize Peak Power during Scan Testing of SoC
(
- Contribution to conference › Paper, not in proceeding
-
Mark
Power Efficient Redundant Execution for Chip Multiprocessors
(
- Contribution to conference › Paper, not in proceeding
-
Mark
Generation of Minimal Leakage Input Vectors with Constrained NBTI Degradation
(
- Contribution to conference › Paper, not in proceeding
-
Mark
On Scan Chain Diagnosis for Intermittent Faults
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Capture Power Reduction for Modular System-on-Chip Test
2009) IEEE/VSI VLSI Design and Test Symposium (VDAT)(
- Contribution to conference › Paper, not in proceeding
-
Mark
Thermal Aware Test Scheduling for Stacked Multi-Chip-Modules
2009) DATE 2009 Friday Workshop on 3D Integration - Technology, Architecture, Design, Automation, and Tes(
- Contribution to conference › Paper, not in proceeding
-
Mark
Fault-Tolerant Average Execution Time Optimization for System-On-Chips
2009) Frontiers of High Performance Embedded Computing(
- Contribution to conference › Paper, not in proceeding
- 2008
-
Mark
Cycle-Accurate Test Power Modeling and its Application to SoC Test Architecture Design and Scheduling
2008) In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 27(5). p.973-977(
- Contribution to journal › Article
-
Mark
An Architecture for Integrated Test Data Compression and Abort-on-Fail Testing in a Multi-Site Environment
(
- Contribution to journal › Article
-
Mark
A reconfigurable power conscious core wrapper and its application to system-on-chip test scheduling
(
- Contribution to journal › Article
-
Mark
Test-Architecture Optimization and Test Scheduling for SOCs with Core-Level Expansion of Compressed Test Patterns
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Core-Level Expansion of Compressed Test Patterns
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
An Integrated System-on-Chip Test Framework
2008) p.439-454(
- Chapter in Book/Report/Conference proceeding › Book chapter
-
Mark
Test Response Compression for Diagnosis in Volume Production
2008) DAC08 Workshop on Diagnostic Services in Network-on-Chips DSNOC(
- Contribution to conference › Paper, not in proceeding
-
Mark
SOC Test Optimization with Compression-Technique Selection
2008) A Workshop in Conjunction with the International Test Conference(
- Contribution to conference › Paper, not in proceeding
-
Mark
On Reduction of Capture Power for Modular System-on-Chip Test
2008) IEEE Workshop on RTL and High Level Testing WRTLT08(
- Contribution to conference › Paper, not in proceeding
- 2007
-
Mark
Protocol Requirements in an SJTAG/IJTAG Environment
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Test Quality Analysis and Improvement for an Embedded Asynchronous FIFO
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Optimized Integration of Test Compression and Sharing for SOC Testing
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A Heuristic for Concurrent SOC Test Scheduling with Compression and Sharing
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
What Impacts Course Evaluation?
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
An Architecture for Combined Test Data Compression and Abort-on-Fail Test
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Extended STAPL as SJTAG Engine
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Combined Test Data Selection and Scheduling for Test Quality Optimization under ATE Memory Depth Constraint
2007) p.221-244(
- Chapter in Book/Report/Conference proceeding › Book chapter
-
Mark
Test Data Truncation for Test Quality Maximization under ATE Memory Depth Constraint
(
- Contribution to journal › Article
-
Mark
Improved Scan Chain Diagnosis
2007) 15th NXP IC Test Symposium(
- Contribution to conference › Paper, not in proceeding
-
Mark
Protocol Requirements in an SJTAG/IJTAG Environment
2007) Nordic Test Forum NTF,2007(
- Contribution to conference › Paper, not in proceeding
- 2006
-
Mark
Cycle-Accurate Test Power Modeling and its Application to SoC Test Scheduling
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Power-Aware Test Planning in the Early System-On-Chip Design Exploration Process
(
- Contribution to journal › Article
-
Mark
System-on-chip test scheduling with reconfigurable core wrappers
(
- Contribution to journal › Article
-
Mark
Combined Test Data Compression and Abort-on-Fail Test
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
High-Quality Low-Cost Test and DfT for an Embedded Asynchronous FIFO
2006) 14th Philips Research IC Test Seminar(
- Contribution to conference › Paper, not in proceeding
- 2005
-
Mark
Abort-on-Fail Based Test Scheduling
(
- Contribution to journal › Article
-
Mark
Remote Boundary-Scan System Test Control for the ATCA Standard
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Multiple Constraints Driven System-on-Chip Test Time Optimization
(
- Contribution to journal › Article
-
Mark
Introduction to Advanced System-on-Chip Test Design and Optimization
2005) In Frontiers in Electronic Testing(
- Book/Report › Book
-
Mark
SOC Test Scheduling with Test Set Sharing and Broadcasting
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Optimization of a Bus-based Test Data Transportation Mechanism in System-on-Chip
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Test Scheduling for Modular SOCs in an Abort-on-Fail Environment
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A Test Data Compression Architecture with Abort-on Fail Capability
2005) IEEE Workshop on RTL and High Level Testing WRTLT(
- Contribution to conference › Paper, not in proceeding
-
Mark
Boundary-Scan Test Control in the ATCA Standard
2005)(
- Contribution to conference › Paper, not in proceeding
-
Mark
Emerging strategies for resource-constrained testing of system chips
2005)(
- Other contribution › Miscellaneous
-
Mark
Combined Test Data Selection and Scheduling for Test Quality Optimization under ATE Memory Depth Constraint
2005) IFIP WG 10.5 Conference on Very Large Scale Integration System-on-Chip {IFIP VLSI-SOC 2005} p.429-434(
- Contribution to conference › Paper, not in proceeding
- 2004
-
Mark
Defect-Aware SOC Test Scheduling
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
An Integrated Technique for Test Vector Selection and Test Scheduling under Test Time Constraint
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Core Selection Integrated in the SOC Test Solution Design-Flow
2004)(
- Other contribution › Miscellaneous
-
Mark
Integrating Core Selection in the SOC Test Solution Design-Flow
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Efficient test solutions for core-based designs
2004) In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 23(5). p.758-775(
- Contribution to journal › Article
-
Mark
Preemptive system-on-chip test scheduling
(
- Contribution to journal › Article
-
Mark
Student-oriented Examination in a Computer Architecture Course
(
- Contribution to conference › Paper, not in proceeding
-
Mark
A Technique for Optimization of System-on-Chip Test Data Transportation
(
- Contribution to conference › Paper, not in proceeding
- 2003
-
Mark
Buffer and Controller Minimization for Time-Constrained Testing of System-On-Chip
2003) 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems DFT03 p.385-392(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
SOC Test Time Minimization Under Multiple Constraints
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Test Resource Partitioning and Optimization for SOC Designs
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
An Efficient Approach to SoC Wrapper Design, TAM Configuration and Test Scheduling
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Optimal System-on-Chip Test Scheduling
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A Reconfigurable Power-conscious Core Wrapper and its Application to SOC Test Scheduling
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
System-on-Chip Test Scheduling based on Defect Probability
2003)(
- Other contribution › Miscellaneous
-
Mark
Defect Probability-based System-On-Chip Test Scheduling
2003) 6th IEEE International Workshop on Design and Diagnostics of Electronics Circuits and Systems DDECS 03,2003 p.25-32(
- Contribution to conference › Paper, not in proceeding
- 2002
-
Mark
Power Constrained Preemptive TAM Scheduling
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Integrated Test Scheduling, Test Parallelization and TAM Design
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Optimal Test Access Mechanism Scheduling using Preemption and Reconfigurable Wrappers
2002)(
- Other contribution › Miscellaneous
-
Mark
An Integrated Framework for the Design and Optimization of SOC Test Solutions
(
- Contribution to journal › Article
-
Mark
An Integrated Framework for the Design and Optimization of SOC Test Solutions
2002) p.21-36(
- Chapter in Book/Report/Conference proceeding › Book chapter
- 2001
-
Mark
An Integrated System-On-Chip Test Framework
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
The Design and Optimization of SOC Test Solutions
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Test Scheduling and Scan-Chain Division Under Power Constraint
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
System-on-Chip Test Parallelization Under Power Constraints
2001)(
- Other contribution › Miscellaneous
- 2000
-
Mark
An Integrated System-Level Design for Testability Methodology An Integrated System-Level Design for Testability Methodology
2000)(
- Thesis › Doctoral thesis (monograph)
-
Mark
Test Infrastructure Design and Test Scheduling Optimization
2000)(
- Other contribution › Miscellaneous
-
Mark
A Technique for Test Infrastructure Design and Test Scheduling
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
System-on-Chip Test Bus Design and Test Scheduling
2000) International Test Synthesis Workshop,2000(
- Contribution to conference › Paper, not in proceeding