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- 2024
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Mark
A Reconfigurable Ferroelectric Transistor as An Ultra-Scaled Cell for Low-Power In-Memory Data Processing
2024) In Advanced Electronic Materials(
- Contribution to journal › Article
-
Mark
Cryogenic Ferroelectricity of HZO Capacitors on a III-V Semiconductor
(
- Contribution to journal › Article
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Mark
Source Design of Vertical III-V Nanowire Tunnel Field-Effect Transistors
(
- Contribution to journal › Article
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Mark
TFET Circuit Configurations Operating below 60 mV/dec
(
- Contribution to journal › Article
- 2023
-
Mark
Electrically active defects in Al2O3-InGaAs MOS stacks at cryogenic temperatures
2023) 2023 IEEE International Integrated Reliability Workshop, IIRW 2023 In IEEE International Integrated Reliability Workshop Final Report(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
High Current Density Vertical Nanowire TFETs With I₆₀ > 1
μ
A/
μ
m
(
- Contribution to journal › Article
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Mark
Self-Heating in Gate-All-Around Vertical III-V InAs/InGaAs MOSFETs
(
- Contribution to journal › Article
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Mark
High-k/InGaAs interface defects at cryogenic temperature
(
- Contribution to journal › Article
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Mark
gm/Id Analysis of vertical nanowire III–V TFETs
(
- Contribution to journal › Article
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Mark
Dynamics of Polarization Switching in Mixed Phase Ferroelectric-Antiferroelectric HZO Thin Films
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Geometric control of diffusing elements on InAs semiconductor surfaces via metal contacts
(
- Contribution to journal › Article
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Mark
Reconfigurable signal modulation in a ferroelectric tunnel field-effect transistor
(
- Contribution to journal › Article
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Mark
Effects of Interface Oxidation on Noise Properties and Performance in III–V Vertical Nanowire Memristors
(
- Contribution to journal › Article
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Mark
Low-Power, Self-Aligned Vertical InGaAsSb NW PMOS With S < 100 mV/dec
(
- Contribution to journal › Article
-
Mark
Sensing single domains and individual defects in scaled ferroelectrics
(
- Contribution to journal › Article
- 2022
-
Mark
Performance enhancement of GaSb vertical nanowire p-type MOSFETs on Si by rapid thermal annealing
(
- Contribution to journal › Article
-
Mark
Hydrogen plasma enhanced oxide removal on GaSb planar and nanowire surfaces
2022) In Applied Surface Science(
- Contribution to journal › Article
-
Mark
Lateral III-V Nanowire MOSFETs in Low-Noise Amplifier Stages
(
- Contribution to journal › Article
-
Mark
As-deposited ferroelectric HZO on a III–V semiconductor
(
- Contribution to journal › Article
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Mark
Directed Self‐Assembly for Dense Vertical III–V Nanowires on Si and Implications for Gate All‐Around Deposition
(
- Contribution to journal › Article
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Mark
Improved Electrostatics through Digital Etch Schemes in Vertical GaSb Nanowire p-MOSFETs on Si
(
- Contribution to journal › Article
-
Mark
A 4F2 Vertical Gate-all-around Nanowire Compute-in-memory Device Integrated in (1T1R) Cross-Point Arrays on Silicon
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Performance, Analysis, and Modeling of III-V Vertical Nanowire MOSFETs on Si at Higher Voltages
(
- Contribution to journal › Article
-
Mark
Integration of Ferroelectric HfxZr1-xO2 on Vertical III-V Nanowire Gate-All-Around FETs on Silicon
(
- Contribution to journal › Article
-
Mark
Improved Endurance of Ferroelectric HfxZr1–xO2 Integrated on InAs Using Millisecond Annealing
(
- Contribution to journal › Article
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Mark
The Effect of Deposition Conditions on Heterointerface-Driven Band Alignment and Resistive Switching Properties
(
- Contribution to journal › Article
-
Mark
Ferroelectric-Antiferroelectric Transition of Hf1- xZrxO2on Indium Arsenide with Enhanced Ferroelectric Characteristics for Hf0.2Zr0.8O2
(
- Contribution to journal › Article
-
Mark
Low-Frequency Noise in Vertical InAs/InGaAs Gate-All-Around MOSFETs at 15 K for Cryogenic Applications
(
- Contribution to journal › Article
- 2021
-
Mark
Design of III-V Vertical Nanowire MOSFETs for Near-Unilateral Millimeter-Wave Operation
2021) 15th European Microwave Integrated Circuits Conference, EuMIC 2020 In EuMIC 2020 - 2020 15th European Microwave Integrated Circuits Conference p.85-88(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Controlling Filament Stability in Scaled Oxides (3 nm) for High Endurance (>106) Low Voltage ITO/HfO2 RRAMs for Future 3D Integration
2021) 2021 Device Research Conference (DRC)(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Increased Breakdown Voltage in Vertical Heterostructure III-V Nanowire MOSFETs with a Field Plate
(
- Contribution to journal › Article
-
Mark
Tuning oxygen vacancies and resistive switching properties in ultra-thin HfO2 RRAM via TiN bottom electrode and interface engineering
(
- Contribution to journal › Article
-
Mark
Millimeter-Wave Vertical III-V Nanowire MOSFET Device-To-Circuit Co-Design
(
- Contribution to journal › Article
-
Mark
Ultra-Scaled AlOx Diffusion Barriers for Multibit HfOx RRAM Operation
(
- Contribution to journal › Article
-
Mark
High-density logic-in-memory devices using vertical indium arsenide nanowires on silicon
(
- Contribution to journal › Article
-
Mark
Doping Profiles in Ultrathin Vertical VLS-Grown InAs Nanowire MOSFETs with High Performance
(
- Contribution to journal › Article
- 2020
-
Mark
Reduced annealing temperature for ferroelectric HZO on InAs with enhanced polarization
(
- Contribution to journal › Article
-
Mark
A phase-correlated duo-binary waveform generation technique for millimeter-wave radar pulses
(
- Contribution to journal › Article
-
Mark
Low-Power Resistive Memory Integrated on III-V Vertical Nanowire MOSFETs on Silicon
(
- Contribution to journal › Article
-
Mark
Tuning of Source Material for InAs/InGaAsSb/GaSb Application-Specific Vertical Nanowire Tunnel FETs
(
- Contribution to journal › Article
-
Mark
Vertical InAs/InGaAsSb/GaSb Nanowire Tunnel FETs on Si with Drain Field-Plate and EOT = 1 nm Achieving Smin= 32 mV/dec and gm/ID= 100 V-1
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Feature size control using surface reconstruction temperature in block copolymer lithography for InAs nanowire growth
(
- Contribution to journal › Article
-
Mark
High-Performance Vertical III-V Nanowire MOSFETs on Si with gm> 3 mS/μm
(
- Contribution to journal › Article
-
Mark
Gate-Length Dependence of Vertical GaSb Nanowire p-MOSFETs on Si
(
- Contribution to journal › Article
-
Mark
Strain mapping inside an individual processed vertical nanowire transistor using scanning X-ray nanodiffraction
(
- Contribution to journal › Article
-
Mark
Compressively-strained GaSb nanowires with core-shell heterostructures
(
- Contribution to journal › Article
-
Mark
Cross-Point Arrays with Low-Power ITO-HfO2 Resistive Memory Cells Integrated on Vertical III-V Nanowires
(
- Contribution to journal › Article
-
Mark
Effects of traps in the gate stack on the small-signal RF response of III-V nanowire MOSFETs
(
- Contribution to journal › Article
-
Mark
Vertical nanowire III–V MOSFETs with improved high-frequency gain
(
- Contribution to journal › Article
-
Mark
Nanowire Tunnel FET with Simultaneously Reduced Subthermionic Subthreshold Swing and Off-Current due to Negative Capacitance and Voltage Pinning Effects
(
- Contribution to journal › Article